QuadPHY PM8385 Manuals
PM8385
QuadPHY RT
Released
4-Port Gigabit Ethernet and 1/2G Fibre Channel Repeater or Retimer
GENERAL
• Extensive per port backplane
•
Programmable receive input
monitoring for loss of signal, error rates,
termination of 100 ohm or 150 ohm
• Supports four physical interfaces for
and link level violations.
differential.
Gigabit Ethernet at 1.25 Gbit/s per
• Supports single-ended or differential
•
Programmable output impedance of
IEEE 802.3z or Fibre Channel physical
125 MHz reference clock for Gigabit
100 ohm or 150 ohm differential.
interfaces at 1.0625 or 2.125 Gbit/s per
Ethernet, or 106.25 MHz reference
Fibre Channel Physical Interface (FC-
clock for Fibre Channel applications.
PI) for repeating or retiming
TEST AND CONTROL
applications.
• Digital loss of link (DLOL) detect pin
• Backplane repeating/retiming signal
HIGH-SPEED INTERFACE
provides status output for monitoring
integrity features enable standards
• High-speed outputs with selectable
individual or multiple links.
compliance, link extension and robust
output amplitude and programmable
• DLOL and optional interrupt pin can be
gigabit-serial operation in the hostile
pre-emphasis per port to counteract
programmed to indicate:
backplane environment.
dielectric losses and allow maximum
•
Analog loss of signal.
• Provides direct connection to high-
reach on printed circuit boards and
speed serial backplanes, coax
•
Excessive 8B/10B code and disparity
cables.
stacking cables, or optical / copper
violations.
• Programmable receive input
Small Form Factor Pluggable (SFP)
•
Fibre Channel comma density.
equalization provides robust data
modules.
recovery of highly degraded input
• Loss of synchronization to detect
• Provides non-blocking cross-bar for
signals.
Gigabit Ethernet or Fibre Channel
protection switching and data bi-cast,
• Minimal board footprint and exceptional
framing errors.
multi-cast or broadcast.
signal integrity achieved:
• Internal packet generator and
• Fast high-speed serial lock times and
comparator features simplify backplane
•
No external components are required
low device latency.
and jitter testing via:
to interface the high-speed signals
• Rate detection/auto-selection between
due to internal AC coupling.
•
Programmable pattern (can be used
1G and 2G Fibre Channel.
with GE high, low and mixed
frequency tests).
BLOCK DIAGRAM
Rx
Rx
Retimer/
Retimer/
2
RDIP[1]
RDIP[2]
Monitor
Monitor
RDIN[1]
SERDES/
10
10
SERDES/
RDIN[2]
2
Reclocker
Reclocker
2
TDOP[1]
TDOP[2]
Tx
Tx
TDON1]
TDON[2]
2
10
Control
Control
10
Cross-bar
Rx
Rx
2
RDIP[0]
Retimer/
Retimer/
RDIP[3]
Monitor
Monitor
RDIN[0]
RDIN[3]
SERDES/
10
10
SERDES/
2
2
Reclocker
Reclocker
TDOP[0]
TDOP[3]
TDON[0]
Tx
Tx
TDON[3]
2
10
Control
Control
10
TCK
Pattern
JT
TMS
Generator/
A
TDI
Comparator
G
TDO
TRSTB
DLOLB
Impedance
Two Wire
CDRU
Control Block
PORT_DLOLB[3:0]
Control
Interface
PORT_2G_RATE[3:0]
INTRB
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PMC-2030741
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC.,
© Copyright PMC-Sierra, Inc. 2003.
Issue 2
AND FOR ITS CUSTOMERS’ INTERNAL USE
All rights reserved.
Document Outline
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