PM5347 Manuals


PM5347
PMC-Sierra,Inc.
S/UNI-155-PLUS
155 Mb/s SATURN User Network Interface for WANs
FEATURES
TRANSMIT SECTION
• Extracts the 16- or 64-byte section 
trace (J0) sequence and the 16- or 64-
• Monolithic SATURN®-compatible 
• Counts transmit cells read from the 
byte path trace (J1) sequence into 
Asynchronous Transfer Mode (ATM) 
transmit FIFO.
internal register banks. 
network interface.
• Inserts a register programmable path 
• Extracts the DCC channels (D1-D3 
• Implements the ATM transmission 
signal label (C2).
and D4-D12) for optional external 
convergence (TC) sublayer for ATM 
• Inserts path B3, path FEBE 
processing.
according to ATM Forum specifications 
indications, line B2, line FEBE 
and ITU-T recommendations using the 
indications, and section B1 to allow 
• Detects Loss Of Signal (LOS), Out Of 
SONET/SDH 155.52 Mb/s format. Also 
performance monitoring at the far end.
Frame (OOF), Loss Of Frame (LOF), 
implements ATM Forum specified 
• Optionally inserts the 16- or 64-byte 
line Alarm Indication Signal (AIS), line 
“Mid-range PHY” rates of 51.52, 25.92 
section trace (J0) sequence and the 16 
Remote Defect Indication (RDI-L), 
and 12.96 Mb/s.
or 64 byte path trace (J1) sequence 
Loss Of Pointer (LOP), path AIS, path 
RDI (RDI-P) and Loss Of Cel  
• Includes on-chip clock recovery and 
from internal register banks.
Delineation (LCD).
clock synthesis at all rates. Clocking 
• Optionally inserts an externally 
can be bypassed for use with external 
generated section user channel (F1), 
• Counts received section B1 errors, line 
clock sources. Operates in master or 
order wire channels (E1, E2) and the 
B2 errors, line FEBEs, path B3 errors 
slave (loop timed) timing modes.
DCC channels (D1-D3 and D4-D12) 
and path FEBEs for performance 
monitoring purposes.
• Provides TTL-compatible inputs and 
via serial interfaces.
outputs. Provides differential pseudo-
• Optionally inserts path AIS, path RDI, 
ECL-compatible serial line side inputs.
line AIS, and line RDI.
APPLICATIONS
• Supports Fiber Optic, Unshielded 
• Optionally inserts register 
• ATM Switching Systems
Twisted Pair and Shielded interfaces.
programmable APS (K1, K2) and 
• ATM Access Systems
• Processes al  SONET/SDH UNI 
synchronization status (Z1) bytes.
• LAN Switches, Hubs and Routers
overhead.
RECEIVE SECTION
• ATM Test Equipment
• Provides access to section and line 
• SONET or SDH ATM Interfaces
datalinks and all additional transport 
• Filters and captures the automatic 
and path overhead to allow additional 
protection switch channel (K1, K2) 
external processing for full SONET/ 
bytes in readable registers and detects 
SDH Network-Node Interface (NNI) 
APS byte failure.
compliance.
• Provides synchronous 8-bit or 16-bit 
BLOCK DIAGRAM
SCI-PHY™ system side interface with 
Line Side
C
System Side
4-cell deep FIFO buffers in transmit 
U
WCLK
S
,
T
and receive paths with parity support.
O
,
T
W
W
K
O
]
O
P
N
K
N
S
K
P
F
E
P
L
L
F
E
:
0
0]
• Inserts and extracts ATM payloads 
B
P
I
S
,
T
,
TL
HCLK
F
C
C
HCLK
I
S
C
F
T
P
T
Y
A
DCL
D
RDI
DCLK
D
OH
OH
O
OH
O
O
OH
OH
O
OH
RDI
P[3
[
3:
A
P
F
F
O
I
K
S
S
S
L
L
T
P
P
I
P
using cel  delineation.
TA
TB
TL
T
TS
T
T
TL
TT
TT
T
TT
TOH
GT
GT
TP
TP
T
TP
TP
T
PO
P
TC
TG
XO
TD
TD
TC
TM
TR
• Provides a generic 8-bit 
microprocessor bus interface for 
Transport 
Path 
Paral el
JTAG Test 
O/H 
O/H 
Input/Output Port
Access Port
configuration, control, and status 
Extract
Extract
monitoring.
TSOC
TDAT[15:0]
• Software-compatible with the PM5345 
TXPRTY[1:0]
S/UNI-155™, PM5346 S/UNI-155-
TRCLK+/-
Transmit
Transmit
TCA
Clock 
Transmit
Transmit
Transmit 
LITE™ and the PM5355 S/UNI-622™.
Line O/H
Path Overhead 
TXD+/-
Recovery 
Section O/H
ATM
ATM 4-Cel  
Processor
Processor
TWRENB
SIPO
Processor
Cell Processor
FIFO
• Provides a standard 5-signal P1149.1 
TXC+/-
TFCLK
Section 
Path 
Drop
Trace 
Trace 
Side
JTAG test port for boundary scan 
Buffer
Buffer
I/F
RXDO+/-
RSOC
board test purposes.
Clock 
RXD+/-
Receive
Receive
Receive 
Receive
Recovery 
Section O/H
Receive
ATM
ATM 4-Cel  
RDAT[15:0]
Path Overhead 
ALOS+/-
SIPO
Line O/H
Processor
Cell Processor
FIFO
• Low power, +5 V CMOS technology.
Processor
Processor
RXPRTY[1:0]
RRCLK+/-
• Packaged in a 208 pin (28mm x 
RCA
RRDENB
28mm) PQFP with 0.5mm pin pitch.
Transport 
Path 
Microprocessor 
RFCLK
O/H 
• Industrial temperature range operation 
O/H 
Interface
Extract
Extract
(-40°C to +85°C).
• Counts received cel s written into the 
/
-
P
S
P
P
P
L
E
B
B
B
receive FIFO, received HCS errored 
+
O
H
P
D
C
T
C
I
S
W
H
0]
0]
U
O
F
LK
O
F
LK
S8
RDI
7:
T
T
F
LF
FL
BYP
LO
LOF
H
HF
C
C
LO
LC
[
7:
AL
RA
LA
H
CS
RCP
SEN
R
S
LRDI
P
WRB
RDB
IN
WCLK
RT
O
HCLK
O
O
O
PYE
D[
A
RS
RG
BU
T
cel s that are discarded, and received 
,
R
 RLO
O
RP
RO
W
RLDCLK
RT
,
RO
GR
RP
RP
O
RT
HCS errored cells that are corrected 
RLD,
RS
D,
and passed through the receive FIFO.
DCLK
RS
RS
PMC-930909 (R7) 
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USEã 1998 PMC-Sierra, Inc. October, 

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