MoBL CY62146ESL Manuals



CY62146ESL MoBL®
4-Mbit (256K x 16) Static RAM
Features
mode reduces power consumption by more than 99% when
deselected (CE HIGH). The input and output pins (IO0 through
■ Very high speed: 45 ns 
IO15) are placed in a high impedance state when: 
■ Wide voltage range: 2.2V–3.6V and 4.5V–5.5V
■ Deselected (CE HIGH) 
■ Ultra low standby power
■ Outputs are disabled (OE HIGH) 
❐ Typical Standby current: 1 μA
■ Both Byte High Enable and Byte Low Enable are disabled 
❐ Maximum Standby current: 7 μA
(BHE, BLE HIGH) 
■ Ultra low active power
■ Write operation is active (CE LOW and WE LOW)
❐  Typical active current: 2 mA at f = 1 MHz
To write to the device, take Chip Enable (CE) and Write Enable
■ Easy memory expansion with CE and OE features
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
■ Automatic power down when deselected
0 through IO7) is written into the location
specified on the address pins (A0 through A17). If Byte High
■ CMOS for optimum speed and power
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
is written into the location specified on the address pins (A0
■ Available in Pb-free 44-pin TSOP II package
through A17).
Functional Description
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
The CY62146ESL is a high performance CMOS static RAM
Byte Low Enable (BLE) is LOW, then data from the memory
organized as 256K words by 16 bits. This device features
location specified by the address pins appears on IO0 to IO7. If
advanced circuit design to provide ultra low active current. This
Byte High Enable (BHE) is LOW, then data from memory
is ideal for providing More Battery Life™ (MoBL®) in portable
appears on IO8 to IO15. See the “Truth Table” on page 10 for a
applications such as cellular telephones. The device also has an
complete description of read and write modes.
automatic power down feature that reduces power consumption
For best practice recommendations, refer to the Cypress 
when addresses are not toggling. Placing the device into standby
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
256K x 16
A5
IO
A
RAM Array
0–IO7
4
W DECODER 
A3
O
SENSE AMPS
IO
A
R
8–IO15
2
A1
A0
COLUMN DECODER
BHE
WE
11
12
13
15
CE
17
A
14
16
A
A
A
A
A
A
OE
BLE
Cypress Semiconductor Corporation

198 Champion Court

San Jose, CA 95134-1709

408-943-2600
Document #: 001-43142 Rev. **
 Revised January 04, 2008
[+] Feedback 

Document Outline



Big size of image:

Please install Flash player from http://get.adobe.com/flashplayer/!

37 37 49 49

Designated trademarks and brands are the property of their respective owners | Disclaimer