MoBL CY62126EV30 Manuals

1-Mbit (64K x 16) Static RAM
Functional Description
■ High speed: 45 ns
The CY62126EV30 is a high performance CMOS static RAM
organized as 64K words by 16 bits[1]. This device features
■ Temperature ranges
advanced circuit design to provide ultra low active current. This
❐ Industrial: –40°C to +85°C
is ideal for providing More Battery Life™  (MoBL®) in portable
❐ Automotive: –40°C to +125°C
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
■ Wide voltage range: 2.2V to 3.6V
consumption when addresses are not toggling. Placing the
■ Pin compatible with CY62126DV30
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE HIGH). The input and
■ Ultra low standby power
output pins (IO0 through IO15) are placed in a high impedance
❐ Typical standby current: 1 μA
state when: 
❐ Maximum standby current: 4 μA
■ Deselected (CE HIGH)
■ Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
■ Outputs are disabled (OE HIGH)
■ Easy memory expansion with CE and OE features
■ Both Byte High Enable and Byte Low Enable are disabled 
■ Automatic power down when deselected
■ Write operation is active (CE LOW and WE LOW)
■ CMOS for optimum speed and power
To write to the device, take Chip Enable (CE) and Write Enable
■ Offered in Pb-free 48-ball VFBGA and 44-pin TSOP II 
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7) is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
is written into the location specified on the address pins (A0
through A15).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 9 for a
complete description of read and write modes.
Logic Block Diagram
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation

198 Champion Court

San Jose, CA 95134-1709

Document #: 38-05486 Rev. *E
 Revised January 5, 2009
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