CY7C1020BN Manuals


 
CY7C1020BN
32K x 16 Static RAM
Features
Functional Description
• High  speed
The CY7C1020BN is a high-performance CMOS static RAM
— t
organized as 32,768 words by 16 bits. This device has an
AA = 12, 15 ns 
automatic power-down feature that significantly reduces
• CMOS for optimum speed/power
power consumption when deselected. 
• Low active power
Writing to the device is accomplished by taking Chip Enable
— 825 mW (max.)
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
• Low CMOS standby power (L version only)
1 through I/O8), is
written into the location specified on the address pins (A0
— 2.75 mW (max.)
through A15). If Byte High Enable (BHE) is LOW, then data
• Automatic power-down when deselected
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
• Independent control of upper and lower bits
Reading from the device is accomplished by taking Chip
• Available in 44-pin TSOP II and 400-mil SOJ
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020BN is available in standard 44-pin TSOP Type
II and 400-mil-wide SOJ packages.
Logic Block Diagram
Pin Configuration
SOJ / TSOP II
DATA IN DRIVERS
Top View
NC  1
44
A5
A
2
43
3
A6
A
3
42
2
A7
A7
A
4
41
OE
1
A6
A
5
40
BHE
0
A5
32K x 16
CE
6
39
BLE
A4
RAM Array
I/O1–I/O8
I/O1
7
38
I/O16
A3
I/O
8
37
2
I/O15
A2
SENSE AMPS
I/O9–I/O16
I/O
9
36
3
I/O14
A1
I/O
10
35
4
I/O13
ROW DECODER 
V
11
34
A
CC
VSS
0
V
12
33
SS
VCC
I/O
13
32
5
I/O12
I/O6
14
31
I/O11
I/O7
15
30
I/O10
COLUMN DECODER
I/O
16
29
8
I/O9
WE
17
28
NC
A15
18
27
A8
BHE
A14
19
26
A9
WE
A13
20
25
A10
8
9
A
A
10
11
12
13
14
CE
A12
21
24
A11
A
A
A
A
A
OE
NC
22
23
NC
BLE
Cypress Semiconductor Corporation

198 Champion Court

San Jose, CA 95134-1709

408-943-2600
Document #: 001-06443  Rev. **
 Revised February 1, 2006
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