CY7C1916BV18 Manuals



CY7C1316BV18, CY7C1916BV18
CY7C1318BV18, CY7C1320BV18

18-Mbit DDR-II SRAM 2-Word
Burst Architecture
Features
Functional Description
■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and
CY7C1320BV18 are 1.8V Synchronous Pipelined SRAMs
■ 300 MHz clock for high bandwidth
equipped with DDR-II architecture. The DDR-II consists of an
■ 2-word burst for reducing address bus frequency 
SRAM core with advanced synchronous peripheral circuitry and
a one-bit burst counter. Addresses for read and write are latched
■ Double Data Rate (DDR) interfaces 
on alternate rising edges of the input (K) clock. Write data is
(data transferred at 600 MHz) at 300 MHz 
registered on the rising edges of both K and K. Read data is
■ Two input clocks (K and K) for precise DDR timing
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
❐ SRAM uses rising edges only
is associated with two 8-bit words in the case of CY7C1316BV18
■ Two input clocks for output data (C and C) to minimize clock 
and two 9-bit words in the case of CY7C1916BV18 that burst
skew and flight time mismatches
sequentially into or out of the device. The burst counter always
starts with a ‘0’ internally in the case of CY7C1316BV18 and
■ Echo clocks (CQ and CQ) simplify data capture in high-speed 
CY7C1916BV18. For CY7C1318BV18 and CY7C1320BV18,
systems
the burst counter takes in the least significant bit of the external
■ Synchronous internally self-timed writes
address and bursts two 18-bit words (in the case of
CY7C1318BV18) of two 36-bit words (in the case of
■ 1.8V core power supply with HSTL inputs and outputs
CY7C1320BV18) sequentially into or out of the device.
■ Variable drive HSTL output buffers
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
■ Expanded HSTL output voltage (1.4V–VDD)
physical pins as the data inputs, D) are tightly matched to the two
■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
output echo clocks CQ/CQ, eliminating the need to capture data
separately from each individual DDR SRAM in the system
■ Offered in both Pb-free and non Pb-free packages
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
■ JTAG 1149.1 compatible test access port
All synchronous inputs pass through input registers controlled by
■ Delay Lock Loop (DLL) for accurate data placement
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
Configurations
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
CY7C1316BV18 – 2M x 8
CY7C1916BV18 – 2M x 9
CY7C1318BV18 – 1M x 18
CY7C1320BV18 – 512K x 36
Selection Guide
Description
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency 
300
278
250
200
167
MHz
Maximum Operating Current 
x8
815
775
705
575
490
mA
x9
820
780
710
580
490
mA
x18
855
805
730
600
510
mA
x36
930
855
775
635
540
mA
Cypress Semiconductor Corporation

198 Champion Court

San Jose, CA 95134-1709

408-943-2600
Document Number: 38-05621 Rev. *D
 Revised June 2, 2008
[+] Feedback 

Document Outline



Big size of image:

Please install Flash player from http://get.adobe.com/flashplayer/!

35 35 48 48

Designated trademarks and brands are the property of their respective owners | Disclaimer