CY7C1910BV18 Manuals



CY7C1310BV18, CY7C1910BV18
CY7C1312BV18, CY7C1314BV18

18-Mbit QDR™-II SRAM 2-Word
Burst Architecture
Features
Functional Description
■ Separate independent read and write data ports
The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and
❐ Supports concurrent transactions
CY7C1314BV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
■ 250 MHz clock for high bandwidth
consists of two separate ports: the read port and the write port to
■ 2-word burst on all accesses
access the memory array. The read port has data outputs to
■ Double Data Rate (DDR) interfaces on both read and write ports 
support read operations and the write port has data inputs to
(data transferred at 500 MHz) at 250 MHz 
support write operations. QDR-II architecture has separate data
inputs and data outputs to completely eliminate the need to
■ Two input clocks (K and K) for precise DDR timing
“turn-around” the data bus required with common IO devices.
❐ SRAM uses rising edges only
Access to each port is accomplished through a common address
■ Two input clocks for output data (C and C) to minimize clock 
bus. The read address is latched on the rising edge of the K clock
skew and flight time mismatches
and the write address is latched on the rising edge of the K clock.
Accesses to the QDR-II read and write ports are completely
■ Echo clocks (CQ and CQ) simplify data capture in high-speed 
independent of one another. To maximize data throughput, both
systems
read and write ports are provided with DDR interfaces. Each
■ Single multiplexed address input bus latches address inputs 
address location is associated with two 8-bit words
for both read and write ports
(CY7C1310BV18), 9-bit words (CY7C1910BV18), 18-bit words
■ Separate port selects for depth expansion
(CY7C1312BV18), or 36-bit words (CY7C1314BV18) that burst
sequentially into or out of the device. Because data can be trans-
■ Synchronous internally self-timed writes
ferred into and out of the device on every rising edge of both input
■ Available in x8, x9, x18, and x36 configurations 
clocks (K and K and C and C), memory bandwidth is maximized
while simplifying system design by eliminating bus
■ Full data coherency, providing most current data
“turn-arounds”.
■ Core VDD = 1.8V (±0.1V); IO VDDQ = 1.4V to VDD
Depth expansion is accomplished with port selects, which
■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
enables each port to operate independently.
■ Offered in both Pb-free and non Pb-free packages
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
■ Variable drive HSTL output buffers
registers controlled by the C or C (or K or K in a single clock
■ JTAG 1149.1 compatible test access port
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1310BV18 – 2M x 8
CY7C1910BV18 – 2M x 9
CY7C1312BV18 – 1M x 18
CY7C1314BV18 – 512K x 36
Selection Guide
Description
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency 
250
200
167
MHz
Maximum Operating Current 
x8
735
630
550
mA
x9
735
630
550
x18
800
675
600
x36
900
750
650
Cypress Semiconductor Corporation

198 Champion Court

San Jose, CA 95134-1709

408-943-2600
Document #: 38-05619 Rev. *F
 Revised June 2, 2008
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