CY7C185 Manuals


 
fax id: 1013
CY7C185
8K x 8 Static RAM
Features
provided by an active LOW chip enable (CE1), an active HIGH
chip enable (CE2), and active LOW output enable (OE) and
• High speed
three-state drivers. This device has an automatic power-down
— 15  ns
feature (CE1 or CE2), reducing the power consumption by 70%
when deselected. The CY7C185 is in a standard 300-mil-wide
• Fast tDOE
DIP, SOJ, or SOIC package.
• Low active power
An active LOW write enable signal (WE) controls the writ-
— 715  mW
ing/reading operation of the memory. When CE1 and WE in-
• Low standby power
puts are both LOW and CE2 is HIGH, data on the eight data
— 220  mW
input/output pins (I/O0 through I/O7) is written into the memory
location addressed by the address present on the address
• CMOS for optimum speed/power
pins (A0 through A12). Reading the device is accomplished by
• Easy memory expansion with CE1, CE2, and OE features
selecting the device and enabling the outputs, CE1 and OE
• TTL-compatible inputs and outputs
active LOW, CE2 active HIGH, while WE remains inactive or
• Automatic power-down when deselected
HIGH. Under these conditions, the contents of the location ad-
dressed by the information on address pins are present on the
Functional Description
eight data input/output pins.
The input/output pins remain in a high-impedance state unless
The CY7C185 is a high-performance CMOS static RAM orga-
the chip is selected, outputs are enabled, and write enable
nized as 8192 words by 8 bits. Easy memory expansion is
(WE) is HIGH. A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configurations
DIP/SOJ/SOIC
Top View
NC
1
28
VCC
A4
2
27
WE
A5
3
26
CE2
A6
4
25
A3
A7
5
24
A2
I/O0
A8
6
23
A1
A9
7
22
OE
INPUT BUFFER
A10
I/O
8
21
A0
1
A11
9
20
CE1
A12
10
19
I/O7
A1
I/O
I/O0
2
11
18
I/O6
A
S
I/O1
I/O
2
12
17
5
P
A
I/O2
I/O4
3
13
16
M
I/O3
GND
I/O
A
14
15
3
4
256 x 32 x 8
A
ARRAY
C185–2
5
 DECODER
NSE A
A
I/O4
6
A
SE
7
ROW
A
I/O
8
5
I/O6
POWER
CE1
CE2
COLUMN DECODER
DOWN
I/O7
WE
OE
0
9
A
10
11
12
C185–1
A
A
A
A
Selection Guide[1]
7C185–15
7C185–20
7C185–25
7C185–35
Maximum Access Time (ns)
15
20
25
35
Maximum Operating Current (mA)
130
110
100
100
Maximum Standby Current (mA)
40/15
20/15
20/15
20/15
Note:
1.
For military specifications, see the CY7C185A datasheet.
Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600
August 12, 1998


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