CY7C1541V18 Manuals



CY7C1541V18, CY7C1556V18
CY7C1543V18, CY7C1545V18

72-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.0 Cycle Read Latency)
Features
Configurations
■ Separate independent read and write data ports
With Read Cycle Latency of 2.0 cycles:
❐ Supports concurrent transactions
CY7C1541V18 – 8M x 8
■ 375 MHz clock for high bandwidth
CY7C1556V18 – 8M x 9
■ 4-word burst for reducing address bus frequency 
CY7C1543V18 – 4M x 18
■ Double Data Rate (DDR) interfaces on both read and write ports 
CY7C1545V18 – 2M x 36
(data transferred at 750 MHz) at 375 MHz 
Functional Description
■ Available in 2.0 clock cycle latency 
The CY7C1541V18, CY7C1556V18, CY7C1543V18, and
■ Two input clocks (K and K) for precise DDR timing
CY7C1545V18 are 1.8V Synchronous Pipelined SRAMs,
❐ SRAM uses rising edges only
equipped with QDR-II+ architecture. Similar to QDR-II archi-
■ Echo clocks (CQ and CQ) simplify data capture in high-speed 
tecture, QDR-II+ SRAMs consists of two separate ports: the read
systems
port and the write port to access the memory array. The read port
has dedicated data outputs to support read operations and the
■ Data valid pin (QVLD) to indicate valid data on the output
write port has dedicated data inputs to support write operations.
QDR-II+ architecture has separate data inputs and data outputs
■ Single multiplexed address input bus latches address inputs 
to completely eliminate the need to “turn-around” the data bus
for both read and write ports
that exists with common IO devices. Each port is accessed
■ Separate port selects for depth expansion
through a common address bus. Addresses for read and write
addresses are latched on alternate rising edges of the input (K)
■ Synchronous internally self-timed writes
clock. Accesses to the QDR-II+ read and write ports are
■ Available in x8, x9, x18, and x36 configurations
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
■ Full data coherency, providing most current data
interfaces. Each address location is associated with four 8-bit
words (CY7C1541V18), 9-bit words (CY7C1556V18), 18-bit
■ Core V
[1]
DD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD 
words (CY7C1543V18), or 36-bit words (CY7C1545V18) that
■ HSTL inputs and variable drive HSTL output buffers
burst sequentially into or out of the device. Because data is trans-
ferred into and out of the device on every rising edge of both input
■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
clocks (K and K), memory bandwidth is maximized while simpli-
■ Offered in both Pb-free and non Pb-free packages
fying system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with port selects, which
■ JTAG 1149.1 compatible test access port
enables each port to operate independently.
■ Delay Lock Loop (DLL) for accurate data placement
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Description
375 MHz
333 MHz
300 MHz
Unit
Maximum Operating Frequency 
375
333
300
MHz
Maximum Operating Current 
x8
1300
1200
1100
mA
x9
1300
1200
1100
x18
1300
1200
1100
x36
1370
1230
1140
Note
1. The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting 
VDDQ = 1.4V to VDD.
Cypress Semiconductor Corporation

198 Champion Court

San Jose, CA 95134-1709

408-943-2600
Document Number: 001-05389 Rev. *F
 Revised March 06, 2008
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