CY7C1529AV18 Manuals



CY7C1522AV18, CY7C1529AV18
CY7C1523AV18, CY7C1524AV18

72-Mbit DDR-II SIO SRAM 2-Word
Burst Architecture
Features
Functional Description
■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
The CY7C1522AV18, CY7C1529AV18, CY7C1523AV18, and
CY7C1524AV18 are 1.8V Synchronous Pipelined SRAMs,
■ 300 MHz clock for high bandwidth
equipped with Double Data Rate Separate IO (DDR-II SIO)
■ 2-word burst for reducing address bus frequency 
architecture. The DDR-II SIO consists of two separate ports: the
■ Double Data Rate (DDR) interfaces 
read port and the write port to access the memory array. The
(data transferred at 600 MHz) at 300 MHz 
read port has data outputs to support read operations and the
write port has data inputs to support write operations. The DDR-II
■ Two input clocks (K and K) for precise DDR timing
SIO has separate data inputs and data outputs to completely
❐ SRAM uses rising edges only
eliminate the need to “turn-around” the data bus required with
■ Two input clocks for output data (C and C) to minimize clock 
common IO devices. Access to each port is accomplished
skew and flight time mismatches
through a common address bus. Addresses for read and write
are latched on alternate rising edges of the input (K) clock. Write
■ Echo clocks (CQ and CQ) simplify data capture in high-speed 
data is registered on the rising edges of both K and K. Read data
systems
is driven on the rising edges of C and C if provided, or on the
■ Synchronous internally self-timed writes
rising edge of K and K if C/C are not provided. Each address
■ DDR-II operates with 1.5 cycle read latency when the DLL is 
location is associated with two 8-bit words in the case of
enabled
CY7C1522AV18, two 9-bit words in the case of CY7C1529AV18,
two 18-bit words in the case of CY7C1523AV18, and two 36-bit
■ Operates similar to a DDR-I device with 1 cycle read latency in 
words in the case of CY7C1524AV18 that burst sequentially into
DLL off mode
or out of the device. 
■ 1.8V core power supply with HSTL inputs and outputs
Asynchronous inputs include an output impedance matching
■ Variable drive HSTL output buffers
input (ZQ). Synchronous data outputs are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
■ Expanded HSTL output voltage (1.4V–VDD)
data separately from each individual DDR-II SIO SRAM in the
■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
■ Offered in both Pb-free and non Pb-free packages
All synchronous inputs pass through input registers controlled by
■ JTAG 1149.1 compatible test access port
the K or K input clocks. All data outputs pass through output
■ Delay Lock Loop (DLL) for accurate data placement
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
Configurations
synchronous self-timed write circuitry.
CY7C1522AV18 – 8M x 8
CY7C1529AV18 – 8M x 9
CY7C1523AV18 – 4M x 18
CY7C1524AV18 – 2M x 36
Selection Guide
Description
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency 
300
278
250
200
167
MHz
Maximum Operating Current 
x8
900
855
800
700
650
mA
x9
900
855
800
700
650
x18
950
880
800
700
650
x36
1080
1000
900
750
650
Cypress Semiconductor Corporation

198 Champion Court

San Jose, CA 95134-1709

408-943-2600
Document #: 001-06981 Rev. *D
 Revised June 14, 2008
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